Error Amplifier Limitations in High Performance Regulator Applications

The specification of load current transient response at the output of a power supply is subject to requirements related not only to the load transient demand itself – specifically load current step magnitude and slew rate – but also to the characteristics of the power supply. In general, the voltage regulator control loop design constitutes an important element and when fast transient response is required with minimal output voltage deviation, one essential rule generally applies: high control loop crossover frequency. The trend in the industry for high performance power supplies with elevated switching frequencies continues apace. Proportionately higher loop crossover frequencies are necessary in part to keep pace with the escalating load transient slew rate demands and in part to reduce the required number and size of relatively expensive reactive filter components. The popularity of voltage mode control and its multiplicity of variants, pervasive in step-down (and, to a lesser extent, stepup) power converters, has placed particularly significant burden on the voltage loop error amplifier (EA) as it provides the compensating gain contribution to mitigate the rapid falloff in gain related to the complex double pole of the LC filter components. Current mode controlled parts present a single-pole response and their amplifier requirements vis-a-vis voltage mode are not as stridently demanding. Most considerations of loop compensation pay scant attention to the effects of error amplifier performance characteristics, specifically gain-bandwidth product (GBW), open-loop DC (or low frequency) gain and phase margin. The error amplifier is usually implemented as an op-amp IC or integrated in a PWM controller or regulator-based solution. The GBW and DC gain parameters are typically specified in the associated datasheet. In turn, it becomes imperative to seek an assessment of the intricacies associated with operation at high control loop crossover frequencies with limited error amplifier bandwidth, a condition where the EA can likely induce an exigent component of phase lag that presages a dramatic impact to overall system stability. The development of realistic predictions to assist the power supply engineer during the control loop design process is facilitated in this application note by appropriate small-signal and bode plot analysis, the validity of which is verified through simulation results. Tangible design guidelines are outlined by reference solely to the compensator stage crossover frequency.